Let’s start with some terminology. Any device that runs a link-layer protocol is a node which includes hosts, routers, switches, and WiFi access points. The communication channels that connect adjacent nodes along the communication path are links.** In order for a datagram to be transferred from source host to destination host, it must be moved over each of the individual links in the end-to-end path. Over a given link, a transmitting node encapsulates the datagram in a link-layer frame and transmits the frame into the link.
Although the basic service of any link layer is to move a datagram from one node to an adjacent node over a single communication link, the details of the provided service can vary from one link-layer protocol to the next. Possible services that can be offered by a link-layer protocol include:
Above is a typical host architecture. The Ethernet capabilities are either integrated into the motherboard chipset or implemented via a low-cost dedicated Ethernet chip. For the most part, the link layer is implemented on a chip called the network adapter, also sometimes known as a network interface controller(NIC). The network adapter implements many link layer services including framing, link access, error detection, and so on. Thus, much of a link-layer controller’s functionality is implemented in hardware.
On the sending side, the controller takes a datagram that has been created and stored in host memory by the higher layers of the protocol stack, encapsulates the datagram in a link-layer frame, and then transmits the frame into the communication link, following the link-access protocol.
On the receiver side, a controller receives the entire frame and extracts the network layer datagram. If the link layer performs error detection, then it is the sending controller that sets the error-detection bits in the frame header and it’s the receiving controller that performs error detection.
While most oof the link layer is implemented in hardware, part of the link layer is implemented in software that runs on the host’s CPU. The softwares implement the higher-level link-layer functionality such as assembling link-layer addressing information and activating the controller hardware. On receiving side, link-layer software responds to controller interrupts, handling error conditions and passing a datagram up to the network layer.
The overall process of the situation is depicted above. At the sending node. data ,D, to be protected against bit error is augmented with error-detection and -correction bits(EDC). Typically, the data to be protected includes not only the datagram passed down from the network layer for transmission across the link, but also link-level addressing information, sequence numbers, and other fields in the link frame header. Both D and EDC are sent to the receiving node in a link-level frame. The receiver will receive D’ and EDC’ since they might differ from D and EDC.
The receiver thus need to determine whether or not D’ is the same as the original D, given it has only D’ and EDC’. Error-detection and -correction techniques allow the receiver to sometime, but not always, detect that bit errors have occurred. Even with the use of error-detection bits there may still be undetected bit errors. More accurate detection might introduce more overhead - more consumption is needed to compute.
We will examine three techniques: parity checks, checksumming methods and cyclic redundancy checks